In recent years, great advances have been made in increasing the power efficiency of analogue-to-digital converters. Particularly efficient implementations are based on a successive approximation register (SAR) architecture.
In a typical successive approximation register analogue-to-digital conversion (SAR ADC) architecture the input voltage is compared against a digital-to-analogue converter (DAC) output voltage using a comparator in several cycles. The input first goes through a sample and hold block. The SAR search logic block executes a search algorithm, which typically performs a binary search. In the first cycle the input is compared against the middle of the ADC range. From the comparator output the most significant bit (MSB) can be determined. In the next cycle MSB−1 is determined. A conversion to N bits normally requires N cycles. The SAR ADC is low in cost and consumes low operating power. The excellent power efficiency of the SAR converter can be attributed both to the inherent efficiency of the binary search algorithm and the simplicity of the required hardware.
High resolution analogue-to-digital converters (ADCs) (>10 bit) with very low power and MS/s sampling rates are popular in wireless sensor nodes to obtain robust wireless communication links. However, the intrinsic accuracy (DAC matching) of a SAR ADC is limited up to 10 or 12b in modern CMOS technologies. Scaling up the device dimensions can improve matching but deteriorates power-efficiency and speed.
A conventional SAR ADC scheme is depicted in FIG. 1. A sample and hold circuit is needed, as well as a comparator, a DAC and a digital SAR controller. The analogue signal Vin enters the sample and hold (S/H) circuit where the signal simply is sampled and held to provide a buffer for the A/D converter. Vin is compared to a reference voltage Vref at the comparator input. The digital comparison result goes to the SAR controller block comprising the search logic. The controller block adjusts the digital control signals in order to narrow the compared voltages. An adjusted digital signal is outputted to a digital-to-analogue converter (DAC). This signal is converted to an adjusted Vref, which is compared to Vin in the comparator. A common implementation of the DAC uses an array of switchable capacitors that are controlled by the SAR controller block.
Analogue imperfections in the SAR ADC converters such as DAC mismatch and comparator offset, introduce errors that are typically mitigated through a calibration. The calibration measures and compensates for the analogue imperfections in the SAR A/D converters. However, most calibrations are implemented off-chip, as the power for the calibration circuit is relatively high when implemented on-chip. Foreground calibration is an alternative choice but it can introduce additional effort (e.g., manual effort) to perform the calibration.
Calibration methods to correct the DAC mismatches in the ADC are discussed, for example, in “Split-ADC Architecture for Deterministic Digital Background Calibration of a 16b 1MS/s ADC” (J. McNeill et al, ISSCC Dig. Tech. Papers, pp. 276-278, February 2005) and “A 12b 22.5/45MS/s 3.0 mW 0.059mm2 CMOS SAR ADC Achieving Over 90 dB SFD” (W. Liu, et al., ISSCC Dig. Tech. Papers, pp. 380-381, February 2010). However, these references propose performing a correction in the digital domain based on an adaptive learning algorithm. This means the errors in the DAC cannot be directly detected, instead they are compensated by minimizing differences in an iterative LMS algorithm. In LMS algorithms, some important coefficients need to be set to a proper value to avoid overshooting and to achieve a certain accuracy. Besides, in these examples, the algorithm can only be performed at the cost of either introducing two ADCs or doubled conversion time, which results in significant overhead in terms of area, speed, and power. Moreover, another important drawback is that the circuitry required for an adaptive learning algorithm is complex. This results in additional significant cost for the calibration circuits in terms of area and power.
Hence, there is a desire for a low-power fully automated on-chip background calibration approach for correcting DAC mismatch.